An Application-Specific Integrated Circuit (ASIC) is an integrated circuit custom designed for a particular use, also referred to as a System on Chip (SoC). A few examples of ASIC implementations may be found in cellular phones, automotive computers, and personal data assistants (PDAs). The mentioned examples have limited functionality and are therefore used to perform specific tasks. A contrasting example to the ASIC design is a microprocessor. Microprocessors are designed to adapt to many purposes.
The first phase of an ASIC design typically begins with a team of design engineers who determine the functional requirements of the ASIC to be built. Once the required functions have been determined, the design team then constructs a description of the ASIC using a hardware description language (HDL). This phase of the fabrication process is usually referred to as the Register Transfer Level (RTL) design. HDL is used to describe the circuit's operation, its design, and tests to verify its operation by means of simulation. A logic synthesis tool, such as Design Compiler™ by Synopsys, may then be used to transform the RTL design into a large collection of lower-level constructs called standard cells.
Standard cells are the basic building blocks of ASICs. Standard cells, typically taken from a library, consist of pre-characterized collections of gates. The standard cells used in the ASIC design are specific to the intended function of the ASIC design. The resulting collection of standard cells and a power grid, providing the necessary electrical connections, is called a gate-level net list. The gate-level net list is processed by a placement tool, which one-by-one places the individual standard cells onto a designated region within the power grid. Standard cells use a variable number of metal layers for local routing within the cell depending on the complexity of the cell design. The placement of the standard cells is subject to a variety of specified constraints. Therefore, a height requirement is typically set upon standard cells such that all standard cells have a height equal to the required height or a multiple thereof.
During the final stages of ASIC fabrication, a routing tool forms the electrical connections between the standard cells and the power grid. Estimations on delays, clock skew, parasitic resistances and capacitances, and power consumptions are also made and used in a final round of testing. During this round of testing, alterations to the design may be made in order to increase the performance of the device. Once the testing is complete, the design is finally released for chip fabrication.
One area of importance when designing ASICs is clock distribution. An ASIC clock distribution network is characterized by layout area used, clock insertion delay and clock skew. Clock skew is a phenomenon seen in synchronous circuits and occurs when a clock signal arrives at different components of the circuit at different times; in other words, when the clock insertion delay from the clock source differs to each component. A clock signal is generated by a clock circuit and is distributed throughout the ASIC in a balanced network of clock buffers and metal routing. Two general architectures for ASIC clock distribution networks are the Clock Trunk and the Clock Tree, each having physical and electrical characteristics which differ, and depending on the application, one clock architecture may be more beneficial to use in an application than another.
The clock trunk architecture incorporates a large central conductor or trunk in its design, which is driven from one or both ends, with smaller branch conductors extending perpendicularly out from the trunk to distribute the clock signal to the ASIC components on either side of the trunk. Because the trunk clock distribution network has unequal metal paths from the clock source to the driven components, it is inherently unbalanced and introduces a small amount of clock skew in the clock distribution due to differing RC delays in the metal paths to each component.
FIG. 1 displays an example of a clock trunk structure 150. Clock trunk structure 150 includes a central conductor 110, comprising smaller branch conductors 113 extending perpendicularly out from the central conductor to distribute the clock signal 112 to the ASIC components on either side of the conductor. The clock signal CLK 112 is initially passed through a buffer 116 resulting in a clock signal CLK′ 117. Signal CLK′ 117 is passed through both sides of the conductor 110 through buffers 115 and 111. Buffer 111 is an optional buffer used to minimize clock skew.
The tree architecture is a balanced clock distribution scheme, having equal paths from the clock source to the components by design. The tree architecture uses a central distribution point, symmetrical branching, buffering and sub-branching to distribute clocks to components. A clock tree may also have a root and a trunk to convey the clock source to the first branching point. The metal conductors in each branch of a clock tree are usually so closely matched as to introduce negligible clock skew into the clock distribution network on their own. However, for a clock tree to exhibit low skew, all of the clock buffers within the network must have closely matched characteristics and the loads presented to these buffers must be balanced. The branched symmetry of clock trees makes them practical to be generated automatically by ASIC tools. Although quick to generate a complete clock network conforming to worst-case skew margins, a major failing of these ASIC tools, is to minimize the clock skew to levels attainable in custom clock tree designs.
FIG. 1A displays a simplified row-based cell layout 100 featuring an embedded clock tree 107. Cell layout 100 comprises two power supply rails VDD 101 and VSS 103, forming a power grid. Standard cells 105 are placed in the power grid between the voltage supply rails 101 and 103. A clock circuit 109 generates a clock signal which is sent to destinations, or nodes, 111, 113, 115 and 117 of the clock tree 107. A clock signal, originating from clock circuit 109, should have the same distance to travel to node 113 as it does to nodes 111, 115, and 117. If the time taken for the clock signal to reach node 113 is greater or less than the time taken to reach nodes 111, 115, or 117, a clock skew is present. The greater the deviation of the time difference reaching each node, the greater the clock skew.
A more detailed view of a clock tree may be seen in FIG. 2A. An H-clock tree 200 is typically used in ASIC designs. Clock tree 200 comprises four leaves, or nodes, 201, 202, 203, and 204. The clock tree 200 is built using a series of metal wires 210 and buffers 211. A clock signal clk is sent through the tree, resulting in a signal clk′ in node 202 and a signal clk″ in node 204.
The timing diagram of FIG. 2B graphically depicts clock signals clk, clk′ and clk″. As may be seen from the timing diagram, the insertion delays of the rising edges of signals clk′ and clk″ are significantly different, causing a skew. Such a difference needs to be addressed in the timing budget of the design.